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Most of the subject matter of this book has previously been available only in the form of research papers and review articles. I have not attempted to refer to all the published papers. The reader may find it advantageous to refer to the references listed.
This monograph condenses the relevant and pertinent literature on blanket and selective CVD of tungsten (W) into a single manageable volume. The book supplies the reader with the necessary background to bring up, fine tune, and successfully maintain a CVD-W process in a production set-up. Materials deposition chemistry, equipment, process technology, developments, and applications are described.
VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends. This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition techniques are discussed. Chapter 4 presents the methods of VLSI lithography and etching. Conducting films are first deposited at the gate definition step; therefore, the issues related to gate metallization are discussed next in Chapter 5.In Chapter 6, contact metallization is elaborated, and Chapter 7 is devoted to multilevel metallization schemes. Long-time reliability is the subject of Chapter 8, which discusses the issues of contact and interconnect electromigration. GaAs metallization is tackled in Chapter 9. The volume concludes with a general discussion of the functions of interconnect systems in VLSI. Materials scientists, processing and design engineers, and device physicists will find the book very useful.
This is the first book to provide guidance on the development and application of metal silicide technology as it emerges from the scientific to the prototype and manufacturing stages.
Issues relating to the high-K gate dielectric are among the greatest challenges for the evolving International Technology Roadmap for Semiconductors (ITRS). More than just an historical overview, this book will assess previous and present approaches related to scaling the gate dielectric and their impact, along with the creative directions and forthcoming challenges that will define the future of gate dielectric scaling technology.

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